In semiconductor devices, components including gate dielectric devices and structures (e.g., metal gates) are frequently included in designs to perform a variety of functions, decrease device size and increase device performance and functionality. Gate dielectric devices may be formed in gate oxides (e.g., MOSFET gate oxides) with varying dimensions and compositions as determined by design and/or functional intent. Some common gate dielectric devices include thick gate oxide regions (e.g., gates with a thick gate dielectric relative to thin gate oxide regions) for connection with input and output (I/O) devices, and thin gate oxide regions (e.g., gates with a thin gate dielectric relative a thick gate oxide region) for connection with logic devices, high performance devices, etc.
Traditionally, formation of gate dielectric devices is achieved through replacement gate methods using aggressive etching techniques. During these processes, a thick gate oxide layer is deposited over the substrate/device followed by deposition of a silicon layer (e.g., a dummy gate layer) upon the thick gate oxide layer. Portions of these layers are then patterned, implanted, and/or selectively etched down to the substrate before application of interfacial layers, high-K gate dielectrics, etc. Once these regions are defined and an insulator has been deposited and polished about them on the substrate, an aggressive etch is performed to remove the dummy gate layer from within the gate regions and/or to remove select remaining portions of the thick gate dielectric from within the gate regions. This aggressive etching processing these regions for deposition and formation of gate structures and/or devices. However, in creating gate dielectric devices in thick gate oxide regions, these methods, particularly aggressive etching, may be difficult to control, resulting in imprecise devices, damaged surfaces, unintentional layer residue, inconsistent etching in device corners, and/or damage to insulator dielectrics or other components of the semiconductor device. Further, in an effort to avoid and/or limit the negative effects of aggressive etching, some processes may stop etching while a small portion of the oxide layer (e.g., a dummy layer, a residue material layer, etc.) remains on the substrate. This residue material may decrease device efficiency and/or performance when it remains buried within the thin gate dielectric of high performance logic devices.
For example, FIG. 1 is a demonstrative illustration of a cross sectional view of a portion of a semiconductor device 100 including a dummy gate 102 formed through known methods. Semiconductor device 100 may include a substrate 110 (e.g., silicon layer) upon which dummy gate 102 is disposed and/or formed. Dummy gate 102 may include a spacer 170 formed on substrate 110 and between portions of a dielectric layer 120. A barrier layer 130 may be formed between spacer 170 and a dummy gate conductor 150 (e.g., poly-Silicon). A residual layer of thick gate oxide 140 (e.g., a dummy layer, silicon dioxide (SiO2), etc.) may remain between gate conductor 150 and substrate 110 as a result limitations in the formation process (e.g., aggressive etching tolerance). Residual layer of thick gate oxide 140 may interfere with and/or limit semiconductor device 100 performance or design considerations. Turning to FIG. 2, a first gate region 202 and a second gate region 204 may be disposed on a substrate 210 of a semiconductor device 200 in accordance with known methods. First gate region 202 and second gate region 204 may both include a residual layer of thick gate oxide 240 which remains from gate formation processes. An interlayer dielectric 222 may separate first gate region 202 and second gate region 204. During formation of semiconductor device 200, first gate region 202 may be formed into a thin gate region (e.g., a region for high performance devices, a region for logic devices, a region with a thin gate dielectric, etc.) and second gate region 204 may be formed into a thick gate region (e.g., a region for input/output devices, a region with a thick gate dielectric region, etc.). However, aggressive etching may be performed on first gate region 202 to form the thin gate region, this aggressive etching which may damage portions of second gate region 204 and require an undesirable residue of gate oxide 240 in first gate region 202.